Recently, a DDR (Double Data Rate) 4 DRAM (Dynamic Random Access Memory) which has faster processing speed than a DDR 3 DRAM has been used. The DDR 4 DRAM has additional functions that are not included in the DDR 3 DRAM, such as a CRC (Cycle Redundancy Cheek) function and DBI (Data Bus Inversion function. Japanese Patent Application Laid-Open No. 2013-73664 discloses the CRC function which is for checking whether an error is included in write data. Japanese Patent Application Laid-Open No. 2011-187153 shows the DB1 function which is for reducing current consumption resulting from data transfer by reversing the logical level of read data or write data that is input or output simultaneously when a given condition is met.
According to the CRC function, the DRAM performs logic operations on write data to generate a CRC code, and compares the generated CRC code with an input CRC code, thereby checking whether an error is included in the write data.
The CRC code is generated based on not only the write data but also an input signal from a data mask terminal. Input signals from the data mask terminal include data mask signals and data bus inversion signals related to the above DBI function.
The DDR 4 DRAM includes a register called a multipurpose register that is separate from a memory cell array. During initialization following power on, a training operation using the multi-purpose register is carried out to minutely adjust read timing.